This invention relates generally to a method for forming vias in a dielectric film, and more particularly to such a method that includes forming vias in a dielectric layer by laser ablation.
Integrated, low inductance capacitors are essential to the operation of high performance, very large scale integrated (VLSI) semi-conductor packages. The integrated capacitors are typically part of a multi-layered ceramic (MLC) power stabilizing interposer containing through vias. Barium strontium titanate (BaSrTiO.sub.3, commonly referred to as BST) is often used as a high dielectric constant material for decoupling capacitors. Typically, the BST dielectric material is deposited on platinum electrodes. Vias must then be formed through the BST film to provide electrical continuity between the platinum electrodes and components mounted on the interposer.
Currently, vias are formed in BST film by use of wet etch solutions which chemically etch the BST. This method includes a photolithography step to create a resist stencil on the surface of the BST film, followed by wet chemical etching of the BST in the desired locations. This method not only requires a considerable length of time to carry out, but is also expensive. A further problem is created because many of the recommended etchants are not selective with respect to the underlying platinum electrode, thus attacking and removing a portion of the electrode in the via formation process. In addition, some of the etchants, for example, aqua regia, hydrochloric acid, and the other strong acids, may present handling and disposal problems which further make the wet etching process undesirable.
The present invention is directed to overcoming the problems set forth above. It is desirable to have a clean, dry method for forming vias in a dielectric film that does not require resist processing, wet etching, or the use of hazardous chemicals. It is also desirable to have such a method that removes the dielectric material from preselected areas without adversely affecting the underlying electrode layer.